Field of the Invention
The invention relates to an asymmetrically blocking power semiconductor component having a mesa edge termination.
The present invention relates in particular to asymmetrically blocking (that is to say blocking on one side), high-voltage-resistant power semiconductor components with a so-called mesa edge termination, that is to say with a chamfer on the side walls. The invention also relates in particular to those power semiconductor components having so-called punch through dimensioning, that is to say with a field stop zone in order to reduce the electrical field. Such power semiconductor components may, for example, be in the form of pin diodes, gate turn-off thyristors (GTOs), insulated gate bipolar transistors (IGBTs) or the like.
A major criterion for the quality of such power semiconductor components is their emitter efficiency. In order to achieve an emitter efficiency which is as high as possible, the emitter zone must be as highly doped as possible. However, at the same time, it is necessary for the space charge zone to run over as long a distance as possible on the wafer surface in switched-off operation. In order to increase the available distance on the wafer surface for the space charge zone, the side edge of the semiconductor body typically has a positive chamfer.
However, as a rule, this measure is insufficient for high-blocking capable power semiconductor components. For this reason, wide parts are typically etched out of the semiconductor surface in the edge area of the power semiconductor components, that is to say outside their active areas. Although the etched shoulders produced in this way further enlarge the free distance available for the space charge zone, the overall charge carrier concentration required for voltage breakdown on the semiconductor surface is, however, at the same time reduced since the emitter zone is in consequence reduced.
The complete removal of the heavily doped emitter zone in the edge area leads, with punch through dimensioning, to very high field strength peaks on the wafer surface in the area of the etched shoulders since the breakdown charge required to achieve the full blocking capabilityxe2x80x94in the case of silicon, this is about 1012 cmxe2x88x922xe2x80x94is no longer present here. If this field strength exceeds the critical breakdown field strength, which is typically between 170 and 220 kV cmxe2x88x921 for silicon, undesirable, that is to say premature, breakdown of the semiconductor structure occurs in the edge area, even at low voltages.
In order to prevent such an undesirable breakdown occurring in the edge area in power semiconductor components of this generic type, it is necessary to ensure that the integral of the ionization on the surface there is always less than in the volume, that is to say the undesirable field peaks of the electrical field must be reduced there.
One conventional method for building up additional charges in the edge area and for reducing the field peaks is to use electroactive passivation layers composed, typically, of amorphous carbon layers containing hydrogen, or of amorphous silicon-carbide layers containing hydrogen. European Patent EP 0 400 178 B1 describes a method for electroactive passivation. The advantage of this method is that charges can be built up actively in the amorphous layer precisely where they can weaken field strength peaks to a certain extent in a self-adjusting manner.
However, this measure on its own is no longer sufficient for the development of very low-loss power semiconductor components.
In particular, the charge density of the surface charges decreases with temperature, so that it is no longer possible to ensure an adequate blocking capability, particularly at very low temperatures.
It is accordingly an object of the invention to provide a power semiconductor component having a mesa edge termination which overcomes the above-mentioned disadvantages of the prior art devices of this general type, whose edge area remains functional even in extreme conditions, and which ensures the full blocking capability of the semiconductor component.
With the foregoing and other objects in view there is provided, in accordance with the invention, a power semiconductor component having a mesa edge termination. The component has a semiconductor body with first and second surfaces. An inner zone of a first conductivity type is disposed in the semiconductor body. A first zone is disposed in the semiconductor body and is connected to the inner zone and is adjacent the first surface of the semiconductor body.
The semiconductor body has an edge area outside of the first zone and areas are at least partially etched out from the first surface and formed in the edge area. A second zone of a second conductivity type is disposed in the semiconductor body and is connected over a large area to the inner zone, and a boundary area between the second zone and the inner zone defines a pn junction. A field stop zone is adjacent the first surface in the edge area. The field stop zone is formed of the first conductivity type and embedded in the semiconductor body, and the field stop zone is connected to the first zone and to the inner zone.
According to the invention, the field stop zones of the same conductivity type as in the inner zone are provided in the edge area underneath the areas (etched shoulders) which are etched out of the semiconductor body. The field stop zones, which are typically connected to the inner zone and to the emitter zone, are adjacent to the etched-polished, damage-free surface of the etched-out shoulders. The dopant concentration in the field stop zones, which is between the concentration in the emitter zone and the concentration in the inner zone, is in this case set so as to produce a decreasing gradient in the concentration profile of the doping from the surface of the etched shoulders into the depth of the semiconductor body. In this way, it is possible even in extreme conditions to ensure that the semiconductor component does not break down in an unintended way before the predetermined breakdown voltage is reached.
The profile of the dopant concentration is set in the edge area such that the breakdown charge results after etching away a minimum thickness, which is necessary to produce an etched-polished, damage-free surface. This is virtually independent of the depth or thickness of the emitter zone. The dopant concentration in the field stop zone, and its depth, must in this case be set such that, with respect to the vertical direction, the surface-related charge carrier density measured from the field stop zone and the inner zone located underneath is approximately the same as the breakdown charge density. The dopant concentration and the amount of charge carriers introduced in the field stop zone can in this case be set or controlled deliberately by ion implantation.
Alternatively, it would also be feasible to provide the field stop zone not only in the edge area, but to dispose it over a large area, in each case under the emitter zone and directly under the etched-out areas in the edge area.
In principle, it is also feasible for the etched-out areas on the wafer surface not to run in the ideal horizontal manner, but to fall away outward at a slight angle of a few degrees.
In this case, it is likewise possible to produce a dopant concentration gradient falling away toward the edge.
In an equivalent way, it is also feasible for the concentration profile of the field stop zone to have a gradient running flat in the lateral direction toward the edge of the power semiconductor component. In this case, corresponding calculations must also be carried out for the laterally averaged surface charge densities.
Furthermore, it is also feasible to provide an electroactive passivation layer in the edge area, as is described in European Patent EP 0 400 178 B1, in addition to providing the the field stop zone.
The invention is particularly suitable for power diodes (pin diodes) with a mesa edge termination, which are used, for example, as freewheeling diodes for IGBTs and GTOs. However, the invention can also be used very advantageously for other asymmetrically blocking power semiconductor components having a mesa edge termination, such as IGBTs, GTOs and the like.
In accordance with an added feature of the invention, the field stop zone, the first zone and the inner zone are spaced apart from one another such that the first zone and the inner zone are isolated in terms of potential.
In accordance with an additional feature of the invention, the field stop zone has a higher dopant concentration than the inner zone and a lower dopant concentration than the first zone.
In accordance with another feature of the invention, the inner zone has a dopant concentration and the field stop zone has a dopant concentration that are set in the edge area such that a surface-related charge during switched-off operation corresponds to a breakdown charge of the power semiconductor component.
In accordance with a further feature of the invention, a dopant concentration of the charge carriers of the first conductivity type in the edge area has a reducing gradient from the first surface in a vertical direction into the semiconductor body.
In accordance with a further added feature of the invention, a dopant concentration of the charge carriers of the first conductivity type in the edge area has a decreasing gradient in the field stop zone in a lateral direction toward an edge of the semiconductor body.
In accordance with a further additional feature of the invention, there is a first electrode. The first zone functions as an additional field stop zone having charge carriers of the first conductivity type and, at the first surface of the semiconductor body is connected to the first electrode. A second electrode is connected to the second zone at the second surface of the semiconductor body.
In accordance with another added feature of the invention, there is a first electrode. The first zone has charge carriers of the second conductivity type and is connected at the first surface to the first electrode. A third zone of the first conductivity type is connected to the second zone at the second surface of the semiconductor body. A second electrode is provided and is connected to the third zone.
In accordance with yet another feature of the invention, there is a buffer layer functioning as an additional field stop zone and is disposed between and spaces the inner zone and the first zone apart from one another.
In accordance with further embodiment of the invention, there is an electroactive passivation layer provided at least on those areas of the first surface which are provided in the edge area.
In accordance with a concomitant feature of the invention, the semiconductor body, the inner zone, the first zone, the second zone, and the field stop zone form a pin diode, an insulated gate bipolar transistor, or a gate turn-off thyristor.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in-,a power semiconductor component having a mesa edge termination, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.